1. Field of the Invention
The present invention relates to a microcontroller system, and particularly, to a clock signal generator circuit in a microcontroller system.
2. Description of the Related Art
The functions in portable equipment such as cameras, portable telephones, and notebook-type personal computers are becoming more diverse. Parts such as microcomputers and CPUs of these devices must be of high performance. The CPUs have changed from 4-bit or 8-bit types to 16-bit or 32-bit types. These high-performance CPUs involve a high processing speed, and therefore, consume a large amount of power. This causes a power problem in portable equipment driven by batteries. It is required to provide a technique for saving power.
The microcontroller system has a CPU (central processing unit), functional blocks, and a clock controller. The clock controller controls an external source clock signal CK, to provide the CPU and functional blocks with clock signals.
Generally, microcontroller systems, in particular, those for portable equipment have a power saving mode such as a standby mode or a sleep mode to save power. Note that, in the standby mode, the clock controller stops all the clock signals, and in the sleep mode, the clock controller stops the clock signal to the CPU.
The standby mode and the sleep mode effectively reduce power consumption because they stop the supply of clock signals. Completely stopping the functional blocks raises a problem in that a timer function, that must continuously monitor time, is also stopped.
To solve this problem, Japanese Unexamined Patent Publication (Kokai) No. 54-117649 has proposed a microcontroller system having a rate changing function.
A semiconductor circuit employing CMOS technology does not constantly consume power. Only when the elements thereof are switched in response to operation clock signals, does a current flow to them to consume power. Namely, power consumption in a CMOS circuit is proportional to the operation frequency.
Accordingly, a clock controller of the CMOS circuit having the rate changing function divides the frequency of a source clock signal by an integer, to provide a rate of, for example, 1/4 that has a period four times longer than the period of the source clock signal. This long-period clock signal is used to operate the elements of the circuit in a power saving mode, to reduce power consumption. Since the functional blocks of the circuit continuously operate even under the power saving mode, the problems of the standby mode and sleep mode never occur. When the CPU and functional blocks of the circuit are not required to operate at a high speed, the rate changing function is used to reduce power consumption.
The rate changing function divides the frequency of a source clock signal at a fixed rate and supplies the frequency divided signal to the CPU and functional blocks. This prior art is incapable of operating, for example, the CPU at a slower speed and a timer block at a faster speed. The prior art must set the frequency dividing rate according to a functional block that requires the fastest operation speed. This results in consuming large power. These problems in the prior art will be explained hereafter in detail with reference to the accompanying drawings.